1. Field of the Invention
The present invention relates to programmable arrays that implement logic functions on an integrated circuit.
2. Description of the Prior Art
In Field Programmable Gate Arrays (FPGAs), routing conductors are used to connect together logic elements, typically through programmable interconnects. A logic element may also be programmable, and is referred to herein as a "programmable function unit" (PFU), which is also known in the art as a "configurable logic block" (CLB) or "configurable logic a element" (CLE); see for example, U.S. Pat. No. 4,870,302. For sequential circuits, some of these programmable function units are storage elements (i.e. registers). These storage elements are generally enabled to store new data through the use of a clock signal, with each register possibly receiving a different clock. In most cases, FPGAs are made at least partially from internal blocks that are more or less identical. The contents of a block includes both the PFUs and the clock routing noted above. This is desirable to facilitate the computer-aided design of the internal blocks themselves, and to ensure proper operation of interconnected blocks after the FPGA has been programmed.
In order to run a sequential circuit at high speed, the skew between a clock arriving at one PFU and the clock arriving at another PFU must be very small. On FPGAs, however, the delay introduced by routing a clock through a programmable interconnect causes a large skew between the time that the clock arrives at one PFU versus the time that same clock arrives at other PFUs. In a typical FPGA architecture as shown in FIG. 1, this problem is circumvented by adding dedicated clock routing conductors to the FPGA. For example, the bondpads 101 and 102 are dedicated to receiving clock signals, and supplying these signals to the dedicated clock conductors 118 and 122, respectively. The conductors 118 and 122 in turn supply column clock conductors 119, 120, 121; and 123, 124, 125, as indicated, which drive each of the PFUs. In addition, the bondpads 103 and 104 similarly provide clocks to each PFU via other dedicated clock conductors, which for simplicity of illustration are not shown. These dedicated clock routing conductors provide very low skew clocks.
However, one problem with this implementation is that large sections of these clock routing conductors tend to be wasted if only a small number of the PFUs on the FPGA are connected to a particular clock signal. These clock routing conductors also tend to be difficult to use for routing other signals if they are not needed for clock distribution. A third drawback is that the access to drive these clock routing conductors from off of the chip tends to be optimized for only a small number of input/output (I/O) bondpads. One known method of economizing on clock distribution conductors is to multiplex the clock distribution lines from the bondpads. For example, the multiplexers 128, 129 and 130 each receive a clock input from bondpads 107 and 108, via conductors 127 and 126, respectively. The multiplexers then select which clock to supply to each of the columns via the conductors 130, 131 and 132. In a typical case, the bondpads 105 and 106 also receive clock signals and supply them to inputs of the multiplexers via distribution lines, which for simplicity of illustration are not shown. In addition, the inputs to the multiplexers can be supplied with a clock signal from other bondpads or from the outputs of one of the PFUs. However, these techniques do not address the limitations noted above.
Therefore, it would be desirable to have an FPGA routing architecture that would allow for the distribution of low skew clocks, as well as other types of global signals, using the same routing resources. It would also be desirable that all, or at least a significant percentage, of I/O bondpads be approximately equivalent for the purpose of driving these global routing resources. The third need is that the global routing be flexible enough for each global signal to be able to drive anywhere from one PFU to all of the PFUs on the FPGA without wasting routing resources.